1. Technical Field
The present invention relates generally to a recovery of a clock signal and in particular to a digital clock recovery circuit. Still more particularly, the present invention relates to a digital clock recovery circuit with phase interpolation.
2. Description of the Related Art
In digital clock recovery, the phase resolution of a digital clock recovery loop is determined by the number of clock phases available. This number of clock phases is usually set by the number of delay elements in a voltage controlled oscillator (VCO) in the form of a ring oscillator. For example, in FIG. 1, a block diagram of a known digital clock recovery circuit 100 is illustrated. Digital clock recovery circuit is in the form of a digital phase-locked loop (DPLL). Digital clock recovery circuit 100 includes a frequency synthesizer 102, a phase detector 104, a digital filter 106, and a phase selection unit 108. Frequency synthesizer 102 is employed to generate a plurality of clock phases. Phase selection unit 108 is employed to select one of the clock phases generated by frequency synthesizer 102 in response to inputs from phase detector 104 through digital filter 106.
To increase resolution within digital clock recovery circuit 100, the number of delay elements within the ring oscillator in frequency synthesizer 102 needs to increase to raise the number of clock phases. The maximum of delay elements, however, may be limited to the frequency of the VCO in combination with the speed of technology. For example, with complimentary metal oxide semiconductor (CMOS) technologies, a limited number of elements may be used depending on the frequency at which the circuit is to run. For example, in a 0.5 micron CMOS technology, ten clock phases can be generated at 400 MHz. However, the task of providing ten clock phases while the frequency increases becomes more challenging, and ultimately reaches a technological limit. Moreover, ten clock phases may not be sufficient to achieve a specific resolution for a particular application. As a result, with current digital clock recovery circuits, the amount of resolution provided by a frequency synthesizer is limited as the frequency at which circuits run increase. Therefore, it would be advantageous to have an improved method and apparatus for recovering a clock signal.